Research

Analog & digital CMOS circuits

My doctoral research at IIT Ropar focuses on mixed-signal integrated circuit design — building the foundational blocks that clock, power, and test modern silicon systems.

Topic 1

High-speed PRBS generators

Design of pseudo-random bit sequence generators (PRBS-7/15/23/31) using LFSR architectures in advanced CMOS nodes for built-in self-test (BIST) of high-speed serial links and SerDes characterisation.

Topic 1

High-speed PRBS generators (Results)

Topic 2

Low-dropout regulators (LDOs)

Capless and output-capacitor-less LDO topologies targeting fast transient response, high PSRR, and low quiescent current — suitable for powering noise-sensitive analog and RF blocks on-chip.

Topic 2

Low-dropout regulators (LDO Results)

Topic 3 (On-Going)

Analog PLL

Fractional N DSM-based phase-locked loop with LC/ring VCO, focused on low in-band phase noise, low reference spur, and robust loop dynamics for clock generation in mixed-signal SoCs.

Topic 4 (On-Going)

Digital PLL (ADPLL)

All-digital PLL architectures using TDC-based phase detection and digitally controlled oscillators — emphasising process portability, area efficiency, and configurability across nodes.

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