Rahul Walia
PhD Scholar · Electrical Engineering

Rahul Walia

Designing the silicon behind modern mixed-signal systems

Indian Institute of Technology Ropar  ·  Rupnagar, Punjab

Doctoral researcher specializing in analog & digital CMOS integrated circuits — building the foundational blocks that clock, power, and test modern silicon: PRBS generators, Low-dropout regulators, and Fractional-N Phase-Locked Loops.

View Research Publications Contact
4
Journal & Conference Papers
5
Patents Filed
6
Courses as TA

// introduction

About Me

I'm a doctoral researcher in the Department of Electrical Engineering at Indian Institute of Technology Ropar (IIT Ropar), working on analog and digital CMOS integrated circuits — including PRBS generators, low-dropout regulators (LDOs), and analog & digital phase-locked loops (PLLs).

I work under the supervision of Dr. Mahendra Sakare and Dr. Devarshi Das. My doctoral research focuses on mixed-signal integrated circuit design — building the foundational blocks that clock, power, and test modern silicon systems.

Prior to joining IIT Ropar, I completed my Master's degree in Electrical Engineering from NITTTR Chandigarh and carried out my thesis work at CSIR-CSIO Chandigarh on "A Parallel Real-Time Seismic Event Detector and Classification of Events Using Machine Learning."

Research Focus
VLSI Circuit Design
Analog & Mixed-Signal ICs
Low-Dropout Regulators
Phase-Locked Loops
PRBS Generators
CMOS Optimization

// current work

Research

My doctoral research at IIT Ropar focuses on mixed-signal integrated circuit design — building the foundational blocks that clock, power, and test modern silicon systems.

Research Overview 1 Research Overview 2
  Topic 1  ·  Completed

High-speed PRBS Generators

Design of pseudo-random bit sequence generators (PRBS-7/15/23/31) using LFSR architectures in advanced CMOS nodes for built-in self-test (BIST) of high-speed serial links and SerDes characterisation. Features programmable interleaved outputs with uncorrelated sequences for comprehensive link coverage.

PRBS Result 1
PRBS Result 2
PRBS Result 3
  Topic 2  ·  Completed

Low-Dropout Regulators (LDOs)

Capless and output-capacitor-less LDO topologies targeting fast transient response, high Power Supply Rejection Ratio (PSRR), and low quiescent current — suitable for powering noise-sensitive analog and RF blocks on-chip. Features a novel dynamic noise injector for enhanced PSRR across frequency.

LDO Result 1
LDO Result 2
  Topic 3  ·  On-Going

Analog Phase-Locked Loop

Fractional-N DSM-based phase-locked loop with LC/ring VCO, focused on low in-band phase noise, low reference spur, and robust loop dynamics for clock generation in mixed-signal SoCs. Targeting high spectral purity and fine frequency resolution for advanced frequency synthesis applications.

Research in Progress
Fractional-N  ·  DSM  ·  LC/Ring VCO
Low Phase Noise  ·  Low Ref Spur
  Topic 4  ·  On-Going

Digital PLL (ADPLL)

All-digital PLL architectures using TDC-based phase detection and digitally controlled oscillators — emphasising process portability, area efficiency, and configurability across nodes. Fractional-N DSM-based all-digital architecture for scalable, process-portable clocking in modern SoC designs.

Research in Progress
ADPLL  ·  TDC  ·  DCO
Process-Portable  ·  All-Digital

// academic background

Education

Doctor of Philosophy (PhD) — Electrical Engineering
Indian Institute of Technology Ropar
2023 — Present
Research Area: Fractional-N Digital Phase-Locked Loops (D-PLLs) & Mixed-Signal IC Design
Master of Technology (M.Tech) — Electrical Engineering
National Institute of Technical Teachers Training & Research, Chandigarh
2020 — 2022
Thesis: A Parallel Real-Time Seismic Event Detector and Classification of Events Using Machine Learning
Bachelor of Technology (B.Tech) — Electrical Engineering
Kurukshetra University, Kurukshetra
2013 — 2016

// scholarly work

Publications

High-performance paper-based DNA-conjugated Ti₃C₂Tₓ bionanoelectrode for rapid point-of-care detection of HPV-16
R. Rawat et al.
IEEE Sensors Journal, vol. 25, no. 9, pp. 15950–15957, May 2025
DOI: 10.1109/jsen.2025.3551745
A Linearity Improved Equalizers for Short-Channel Communication Links
P. Singh, R. Walia, R. Nagulapalli and M. Sakare
35th Irish Signals and Systems Conference (ISSC), Belfast, UK, 2024
DOI: 10.1109/ISSC61953.2024.10603313
A Resistorless Active Inductor Based CTLE
P. Singh, R. Walia, R. Nagulapalli, and M. Sakare
VDAT 2025, Chandigarh, India
A parallel signal detector approach for detection of human activities using multiple seismic sensors
R. Walia, M. Singh, P. Verma, and R. Ghosh
Lecture Notes in Electrical Engineering, pp. 563–576, 2024
DOI: 10.1007/978-981-99-6855-8_43
An equalizer and method of operation thereof
M. Sakare, P. Singh, R. Walia, R. S. Nagulapalli
Indian Patent Application No. 202311081865  ·  Filed Dec 1, 2023
Indian Patent
Equalizer and method of operation thereof
M. Sakare, P. Singh, R. Walia, R. S. Nagulapalli
U.S. Patent Application No. 18/615,959  ·  Filed Mar 25, 2024
US Patent
A linearity improved equalizers for short-channel communication links
M. Sakare, P. Singh, R. Walia, R. Nagulapalli
Indian Patent Application No. 202411043124  ·  Filed Jun 3, 2024
Indian Patent
Method for enhancing power supply rejection ratio in low dropout regulators using a dynamic noise injector
M. Sakare, R. Walia, P. Singh, R. Nagulapalli
Indian Patent Application No. 202511021155  ·  Filed Mar 8, 2025
Indian Patent
Programmable interleaved PRBS generator integrated circuit with uncorrelated outputs
M. Sakare, P. Singh, R. Walia, R. Nagulapalli, S. Chouksey
Indian Patent Application No. 202511024272  ·  Filed Mar 18, 2025
Indian Patent

// academic service

Teaching Experience

Code Course Title Role Semester
EE659 Radio Frequency Integrated Circuits Teaching Assistant II Sem · AY 2025–26
EE533 CMOS Analog IC Design Teaching Assistant I Sem · AY 2025–26
EE533 Circuit Simulation Lab Teaching Assistant I Sem · AY 2025–26
EE663 Frequency Synthesizers, Clock and Data Recovery Circuits Teaching Assistant II Sem · AY 2024–25
EE302 Analog Circuits Laboratory Teaching Assistant I Sem · AY 2024–25
GE108 Basic Electronics Teaching Assistant II Sem · AY 2023–24

Work Experience

Teaching Assistant
Indian Institute of Technology Ropar
August 2023 – Present
Assisting in lab sessions, tutorials, and grading for undergraduate and postgraduate courses in Analog IC Design, RF Circuits, and Electronics. Supporting students in circuit simulation and verification workflows.
Research Intern
CSIR-CSIO Chandigarh
September 2021 – November 2022
Developed a parallel real-time seismic event detection system with classification using machine learning techniques. Conducted research on human activity detection using multiple seismic sensors, resulting in a conference publication in Lecture Notes in Electrical Engineering.

// get in touch

Contact

Email
rahul.23eez0004@iitrpr.ac.in
Address
Department of Electrical Engineering
Indian Institute of Technology Ropar
Rupnagar, Punjab – 140001, India
Office
Lab 302, J.C. Bose Block
IIT Ropar